1. Field of the Invention
The present invention relates to an intermediate z-interface-board to accept development processes, such as bump bonding an infrared focal plane array (FPA) onto a stacked electronic modules.
2. Description of the Prior Art
Substrates such as multiple silicon chips or ceramic boards may be stacked and integrated using z-technology concepts to achieve modules with a high density of electronic circuitry. In this way, electronic circuits are constructed within a three dimensional framework, which includes the z-direction. Z-plane modules may be used for such applications as visible and infrared focal plane arrays (FDA), computer memory modules and infrared image simulation.
For example, in a FPA, z-plane modules perform signal processing functions on the outputs of a detector element array. The chip substrates are set along the z-axis with exposed electrical leads in order to allow the signal processing circuitry or detector arrays to be mounted on the module. The detector array is often bump bonded to the z-module. The detectors may also be bonded onto each board, or a small assembly of boards, before stacking and gluing the boards into a large array of detectors. However, it is very difficult to perform such process development as indium bump formation and bonding on the edge of a board. Conventional semiconductor processing equipment is constructed to handle flat surfaces such as wafers, not the bulky cubes or tall boards formed by z-plane stacking techniques. There exists a need in the art to provide a flat wafer-like surface to accept conventional process development methods such as photoprocessing i.e., photoresist masking, and indium bump bonding for a z-plane module.
The following patents mostly describe the construction of prior devices using concepts based on the z-plane. None of the patents either address or appreciate the need for performing process development on a flat wafer-like surface instead of the edges of the substrate in a z-plane module when using conventional semiconductor processing equipment.
U.S. Pat. No. 5,111,050 issued to Nevil Q. Maassen et al. on May 5, 1992, describes a radiation detector assembly with a monolithic FPA platform comprised of an A1N material because of its thermal contraction characteristics.
U.S. Pat. No. 5,104,820 issued to Tiong C. Go et al. on Apr. 14, 1992, describes using selective etching to adapt readily available IC wafers for stacking. Go et al. also describe metallization techniques for forming electrical contacts on the access plane of the stack.
U.S. Pat. No. 5,092,036 issued to William C. Hu et al. on Mar. 3, 1992, describes an interconnect pad for micro-circuitry having an array of ultra-tall indium bump columns. The pad contains an array of metal tubes which extend from each side of the pad. The pad is immersed in molten indium which fills the tubes. The pad is then mated with indium bumps on a chip. Pressure is applied to cold weld the indium filled tubes to the indium bumps.
U.S. Pat. No. 5,075,238 issued to Allen L. Solomon on Dec. 24, 1991, describes a method for constructing an infrared detector array directly upon a detector interface device. The crystalline film of the detector is formed on a substrate to form a thermally stable interface between the detector elements and the z-stacked modules.
U.S. Pat. No. 5,072,331 issued to Alan G. Thiele et al. on Dec. 10, 1991, describes a secure circuit structure comprising a pair of opposed substrates that are indium bump bonded.
U.S. Pat. No. 5,015,858 issued to Frank L. Augustine et al. on May 14, 1991, describes a focal point array having an interconnect bump of high thermal resistivity to interconnect the detector and the readout of the array. Perforating transverse vias are used to increase the thermal resistance of the bump. The detector and readout are connected by conventional indium bumps.
U.S. Pat. No. 4,706,166 issued to Tiong C. Go on Nov. 10, 1987, describes forming indium bonding bumps at appropriate points on the access plane of a stack of chips to allow for electrical bonding by matching bumps on the access plane to those on a corresponding substrate surface.
U.S. Pat. No. 4,672,737 issued to John C. Carson et al. on Jun. 16, 1987, describes depositing a passivation layer on the access plane of a stack of semiconductor chips with integrated circuitry, and then lapping the edge of the chips in order to uncover the electrical leads to allow for the placement of photo-detectors along the access plane. It should be noted that U.S. Pat. Nos. 4,672,737, 4,646,128, 4,551,629 and 4,525,921 are all related sibling applications.
U.S. Pat. No. 4,646,128 issued to John C. Carson et al. on Feb. 24, 1987, also describes depositing a passivation layer on the access plane of a stack of semiconductor chips with integrated circuitry, and then lapping the edge of the chips in order to uncover the electrical leads. Thin filmed metallization is performed on the access plane to make electrical connection with the contact points formed as part of the integrated circuitry on the substrates.
U.S. Pat. No. 4,617,160 issued to Robert J. Belanger et al. on Oct. 14, 1986, describes forming stacks of thin circuitry-carrying layers by exerting pressure on a set of aligned chips and epoxy. A thermo-setting adhesive applied between the layers is cured while the stacked chips are set within a fixed-size cavity.
U.S. Pat. No. 4,551,629 issued to John C. Carson et al. on Nov. 5, 1985, describes depositing a passivation layer on the access plane, and then lapping the edge of the chips in order to uncover the metal leads to allow for the placement of photodetectors along the access plane.
U.S. Pat. No. 4,525,921 issued to John C. Carson et al. on Jul. 2, 1985, also describes depositing a passivation layer on the access plane, and then lapping the edge of the chips in order to uncover the metal leads. Metallization is performed on the access plane to contact the appropriate leads on the access plane.
Japanese Kokai No. 03-38084 filed by Sharp Corp. for Yamamura and published on Feb. 19, 1991, describes using conductive particles to achieve a stable connection between electrodes on circuit boards by pressing together bump electrodes on corresponding circuit boards.
Japanese Kokai No. 63-300589 filed by Sharp Corp. for Hosokawa and published on Dec. 7, 1988, describes a multi-layer memory structure in which additional memory can be connected by stacking additional memory substrates to terminals on the substrates.
GB application No. 2,250,138 filed by American Telephone and Telegraph Company for Wayne H. Miller and published on May 27, 1992, describes an arrangement by which individual circuits are routed within a parallel stack of circuit boards by providing staggered terminals on the circuit boards. Circuits routed through these terminals are shifted in position at each layer in the stack.
GB specification No. 1,443,338 filed by Bunker Ramo Corporation for Howard Lee Parks and published on Jul. 21, 1992, describes a method of fabricating a plurality of spaced, electrically insulated through-connections in a predetermined pattern in a conductive sheet by precision stamping. The reference is directed towards stacking and interconnecting wafers in the direction, and not towards interfacing a z-plane module with other electronic components.
While these and other patents disclose circuitry modules using concepts of z-technology, the known prior art does not disclose or suggest the use of the interface board of the present invention to adapt conventional semiconductor processing equipment for use with z-plane modules. For example, none described using an interface board to accept processing such as photoprocessing and indium bump bonding for a stacked z-plane module. None of the above patent references, either alone or in combination with one another, is seen to describe the instant invention as claimed.